Piece Wise Linear Performance Modeling of Submicronic Cmos Library

Shortening of design cycles is currently obtained by designing digital systems at gate or cell level, using precharacterized gate or cell delays to speed up the performance analysis. Modeling timing library format is one of the most difficult task of library designers. We present in this paper a piece wise linear approximation of the delay performance equations of submicronic CMOS library, considering input to output coupling, loading and input wave form induced non linearity. Application is given to a 0.25μm CMOS process for which linear performance equations are deduced for the generally used design range. Limits of linear representations are clearly identified. Validations are obtained through comparison with Spice simulations.